The present invention relates to a content addressable memory chip (or a content addressable memory device).
In a content addressable memory chip (or a content addressable memory device), a configuration which allows a high speed search with little error has been known from the past.
In Patent Literature 1 (Published Japanese Unexamined Patent Application No. Hei 07 (1995)-282587), match lines of a content addressable memory (CAM) circuit are hierarchized and a signal of a match line 31 of the first hierarchy is stored in latch circuits 306, 307, and 308. Using the signal 51 of the latch circuits 306, 307, and 308, a match line 34 of the second hierarchy is discharged during the period of precharge of the match line 31 of the first hierarchy. The match line 34 of the second hierarchy is precharged during the period of discharge of the match line 31 of the first hierarchy.
A semiconductor device 101 disclosed by Patent Literature 2 (Published Japanese Unexamined Patent Application No. 2009-26350) comprises a first control line ML1 in which a signal based on stored data in a first memory circuit CM1 appears; a first characteristic adjustment circuit CL1 which adjusts a read property to the signal appeared in the first control line ML1; a second control line MLT in which a signal based on stored data in a second memory circuit CM1T appears; a second characteristic adjustment circuit CLT which adjusts a read property to the signal appeared in the second control line MLT; and a control signal generating circuit 11 which generates a control signal based on the adjustment result by the second characteristic adjustment circuit CLT. The first characteristic adjustment circuit CL1 adjusts the read property to the signal appeared in the first control line ML1 based on the control signal, and a power supply voltage different from the one supplied to the first memory circuit CM1 is supplied to the second memory circuit CM1T.
In a semiconductor memory device disclosed by Patent Literature 3 (Published Japanese Unexamined Patent Application No. Hei 07 (1995)-14391), a memory matrix employed is divided into four memory matrix sub-blocks in total in the bit column direction, such as a first memory matrix sub-block comprised of word memories MW1a-MW128a. Each memory matrix sub-block has shifted timing in searching time according to corresponding enable timing signals SEa-SEd. Consequently, the peak current in the searching time is distributed, and a peak maximum current is reduced.    (Patent Literature 1) Published Japanese Unexamined Patent Application No. Hei 07 (1995)-282587    (Patent Literature 2) Published Japanese Unexamined Patent Application No. 2009-26350    (Patent Literature 3) Published Japanese Unexamined Patent Application No. Hei 07 (1995)-14391